W25S243A Datasheet, PDF (5/17 Pages) Winbond – 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Preliminary W25S243A
Truth Table, continued
CYCLE
ADDRESS
USED
CE1
CE2
CE3 ADSP ADSC ADV
OE DATA WRITE*
Begin Write
Current
X
X
X
1
1
1
X
Hi-Z Write
Begin Write
Current
1
X
X
X
1
1
X
Hi-Z Write
Begin Write
External
0
1
0
1
0
X
X
Hi-Z Write
Continue Write
Next
X
X
X
1
1
0
X
Hi-Z Write
Continue Write
Next
1
X
X
X
1
0
X
Hi-Z Write
Suspend Write
Current
X
X
X
1
1
1
X
Hi-Z Write
Suspend Write
Current
1
X
X
X
1
1
X
Hi-Z Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to
the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup
the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings are
met.
WRITE TABLE
READ/WRITE FUNCTION
Read
Read
Write byte 1 I/O1−I/O8
Write byte 2 I/O9−I/O16
Write byte 2, byte 1
Write byte 3 I/O17−I/O24
Write byte 3, byte 1
Write byte 3, byte 2
Write byte 3, byte 2, byte 1
Write byte 4, I/O25−I/O32
Write byte 4, byte 1
Write byte 4, byte 2
Write byte 4, byte 2, byte 1
Write byte 4, byte 3
Write byte 4, byte 3, byte 1
Write byte 4, byte 3, byte 2
Write byte 4, byte 3, byte 2, byte 1
Write byte 5, I/O33−I/O40
Write byte 5, byte 1
GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1
1
1
X
X
X
X
X
X
X
X
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
0
1
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
0
1
1
1
0
Publication Release Date: November 1998
-5-
Revision A1