W25S243A Datasheet, PDF (3/17 Pages) Winbond – 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Preliminary W25S243A
PIN DESCRIPTION
SYMBOL
A0−A15
I/O1−I/O64
CLK
CE1, CE2, CE3
GW
BWE
BW1− BW8
OE
ADV
ADSC
ADSP
ZZ
FT
TYPE
Input, Synchronous
I/O, Synchronous
Input, Clock
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Static
LBO
Input, Static
VDDQ
VSSQ
VDD
VSS
RSV
NC
DESCRIPTION
Host address
Data Inputs/Outputs
Processor host bus clock
Chip enables
Global write
Byte write enable from cache controller
Host bus byte enables used with BWE
Output enable input
Internal burst address counter advance
Address status from Chip Set
Address status from CPU
Snooze pin for low-power state, internal pull low
Connected to VSSQ: Device operates in flow-
through (non-pipelined) mode.
Connected to VDDQ or unconnected: Device
operates in pipelined mode.
Lower address burst order
Connected to VSSQ: Device is in linear mode.
Connected to VDDQ or unconnected: Device is in
non-linear mode.
I/O power supply
I/O ground
Power supply
Ground
Reserved pin, don't use these pins
No connection
Publication Release Date: November 1998
-3-
Revision A1