W982516BH Datasheet, PDF (8/43 Pages) Winbond – 4M X 4 BANKS X 16 BIT SDRAM

W982516BH
AC Characteristics and Operating Condition
(Vcc = 3.3V ±0.3V, TA = 0 to 70°C for -7/-75/75L, TA = -40 to 85°C for 75I ; Notes: 5, 6, 7, 8)
PARAMETER
SYM.
Ref/Active to Ref/Active Command Period
t_RC
Active to Precharge Command Period
t_RAS
Active to Read/Write Command Delay Time
t_RCD
Read/Write(a) to Read/Write(b) Command
t_CCD
Period
Precharge to Active Command Period
t_RP
Active(a) to Active(b) Command Period
t_RRD
Write Recovery Time
CL* = 2
t_WR
CL* = 3
CLK Cycle Time
CL* = 2
t_CK
CL* = 3
CLK High Level Width
CLK Low Level Width
Access Time from CLK
t_CH
t_CL
CL* = 2
t_AC
CL* = 3
Output Data Hold Time
t_OH
Output Data High Impedance Time
t_HZ
Output Data Low Impedance Time
t_LZ
Power-down Mode Entry Time
t_SB
Transition Time of CLK
t_T
(Rise and Fall)
Data-in Set-up Time
t_DS
Data-in Hold Time
t_DH
Address Set-up Time
t_AS
Address Hold Time
t_AH
CKE Set-up Time
t_CKS
CKE Hold Time
t_CKH
Command Set-up Time
t_CMS
Command Hold Time
t_CMS
Refresh Time
t_REF
Mode Register Set Cycle Time
t_RSC
*CL = CAS Latency
-7
(PC133, CL2)
MIN.
MAX.
56
40
100000
15
1
15
15
7.5
7
7.5
1000
7
1000
2.5
2.5
5.4
5.4
3
3
7
0
0
7
0.5
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
14
-75/75L/75I
(PC133, CL3)
MIN.
MAX.
65
45
100000
20
1
20
15
10
7.5
10
1000
7.5
1000
2.5
2.5
6
5.4
3
3
7.5
0
0
7.5
0.5
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
15
UNIT
nS
Cycle
nS
mS
nS
-8-