W982516BH Datasheet, PDF (25/43 Pages) Winbond – 4M X 4 BANKS X 16 BIT SDRAM

Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8)
W982516BH
CLK
CS
RAS
CAS
WE
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRCD
tRC
tRAS
tRCD
tRP
tRAS
tRAS
tRP
tRCD
BS0
BS1
A10
RAa
A0-A9,
RAa
A11,12
DQM
CKE
DQ
Bank #0 ^Active
Bank #1
Bank #2
Idle
Bank #3
CAx
ax0 ax1
tRRD
Write
RBb
RBb
CBy
ax4 ax5 ax6 ax7 by0 by1 by2 by3
tRRD
Active
Precharge
Write
RAc
RAc
CAz
by4 by5 by6 by7 CZ0 CZ1 CZ2
Active
Write
Precharge
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Publication Release Date: December 13, 2001
Revision A2