W982516BH Datasheet, PDF (23/43 Pages) Winbond – 4M X 4 BANKS X 16 BIT SDRAM

W982516BH
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
CLK
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
RAS
CAS
tRC
tRAS
tRP
tRP
tRAS
tRC
tRAS
tRC
tRP
WE
BS0
BS1
A10
tRCD
RAa
tRCD
RBb
tRCD
RAc
A0-A9, _RAa
CAx
A11,12
DQM
RBb
CBy
RAc
CAz
CKE
DQ
tRRD
tAC
tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1
tRRD
tAC
by4 by5 by6 by7
CZ0
Bank #0 ^Active
Bank #1
Bank #2
Idle
Bank #3
Read
Precharge
Active
Precharge
Read
Active
Read
Precharge
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Publication Release Date: December 13, 2001
Revision A2