W9725G6JB Datasheet, PDF (8/87 Pages) Winbond – 4M  4 BANKS  16 BIT DDR2 SDRAM

6. BLOCK DIAGRAM
W9725G6JB
CLK
CLK
CKE
CS
RAS
CAS
WE
DLL
CLOCK
BUFFER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
A0
A9
A11
A12
BA0
BA1
ADDRESS
BUFFER
MODE
REGISTER
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
PREFETCH REGISTER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE: The cell array configuration is 8192 * 512 * 16
ODT
ODT
CONTROL
DQ0
|
DQ15
LDQS
LDQS
UDQS
UDQS
LDM
UDM
Publication Release Date: Nov. 29, 2011
-8-
Revision A02