W9725G6JB Datasheet, PDF (45/87 Pages) Winbond – 4M  4 BANKS  16 BIT DDR2 SDRAM

W9725G6JB
9.11.2 AC Characteristics and Operating Condition for -25/25I/25A/25K/-3 speed grade
Notes: 1-3 and 45-47 apply to the entire table
SYM.
tRCD
tRP
tRC
tRAS
tRFC
tREFI
SPEED GRADE
Bin(CL-tRCD-tRP)
PARAMETER
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Auto Refresh to Active/Auto Refresh command
period
-40°C ≤ TCASE ≤ 85°C*
Average periodic
refresh Interval
0°C < TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
95°C < TCASE ≤ 95°C*
DDR2-800
(-25/25I/25A/25K)
5-5-5/6-6-6
MIN. MAX.
12.5

12.5

52.5

40
70000
75


7.8

7.8

3.9

3.9
DDR2-667
(-3)
5-5-5
UNITS²⁵ NOTES
MIN. MAX.
15

nS
23
15

nS
23
55

nS
23
40
70000 nS
4,23
75

nS
5


μS
5

7.8
μS
5

3.9
μS
5,6


μS
5,6
tCCD _{CAS to CAS command delay}
tCK(avg) @ CL=3
tCK(avg) Average clock period
tCK(avg) @ CL=4
tCK(avg) @ CL=5
tCK(avg) @ CL=6
tCH(avg) Average clock high pulse width
tCL(avg) Average clock low pulse width
tAC _{DQ output access time from CLK/ CLK}
2

5
8
3.75
8
2.5
8
2.5
8
0.48 0.52
0.48 0.52
-400
400
2
5
3.75
3

0.48
0.48
-450

8
8
8

0.52
0.52
450
nCK
nS
nS
nS
nS
tCK(avg)
tCK(avg)
pS
30,31
30,31
30,31
30,31
30,31
30,31
35
tDQSCK _{DQS output access time from CLK / CLK}
-350
350
tDQSQ DQS-DQ skew for DQS & associated DQ signals

200
tCKE CKE minimum high and low pulse width
3

tRRD Active to active command period for 1KB page size
7.5

tFAW Four Activate Window for 1KB page size
35

tWR Write recovery time
15

tDAL Auto-precharge write recovery + precharge time
WR + tnRP 
tWTR Internal Write to Read command delay
7.5

tRTP Internal Read to Precharge command delay
7.5

tIS (base) Address and control input setup time
175

-400

3
7.5
37.5
15
WR + tnRP
7.5
7.5
200
tIH (base) Address and control input hold time
250

275
tIS (ref) Address and control input setup time
375

400
tIH (ref) Address and control input hold time
375

tIPW Address and control input pulse width for each input
0.6

tDQSS
DQS latching rising transitions to associated clock
edges
-0.25 0.25
tDSS DQS falling edge to CLK setup time
0.2

tDSH DQS falling edge hold time from CLK
0.2

tDQSH DQS input high pulse width
0.35

tDQSL DQS input low pulse width
0.35

400
0.6
-0.25
0.2
0.2
0.35
0.35
400
240












0.25




pS
35
pS
13
nCK
7
nS
8,23
nS
23
nS
23
nCK
24
nS
9,23
nS
4,23
pS
10,26,
40,42,43
pS
11,26,
40,42,43
pS
10,26,
40,42,43
pS
11,26,
40,42,43
tCK(avg)
tCK(avg) 28
tCK(avg) 28
tCK(avg) 28
tCK(avg)
tCK(avg)
* -40°C ≤ TCASE ≤ 85°C is for 25I/25A/25K grade only, 95°C < TCASE ≤ 105°C is for 25K grade only.
- 45 -
Publication Release Date: Nov. 29, 2011
Revision A02