W83176R-732 Datasheet, PDF (8/11 Pages) Winbond – WINBOND 2DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

W83176R-732
8. SPECIFICATIONS
8.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs
must always be tied to an appropriate logic voltage level (Ground or VDD).
SYMBOL
VDD, AVDD
T_STG
T_B
T_A
PARAMETER
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature
Operating Temperature
RATING
-0.5V to +3.6V
-65°C to +150°C
-55°C to +125°C
0°C to +70°C
8.2 A.C. Characteristics
VDD = AVDD = 2.5V ±5 %, T_A = 0°C to +70°C, Test load = 10 pF
PARAMETER
SYM. MIN. TYP.
Operating Clock
Frequency
F_IN
100
Input Clock Duty Cycle
Dtin
40
Dynamic Supply Current Idd
Cycle to Cycle Jitter
C-
Cjitter
Output to Output Skew Tskew
Output Clock Rise Time
Tor
650
Output Clock Fall Time
Tof
650
Output Clock Duty Cycle Dtot
45
Output Differential-pair
Crossing Voltage
Voc
(VDD/2) VDD/
-0.2
2
MAX. UNITS TEST CONDITIONS
200 MHz
60
%
300
mA Fin = 100 to 200 MHz
200
pS Fout = 100 to 200 MHz
100
pS Fout = 100 to 200 MHz
950
pS Fout = 100 to 200 MHz
950
pS Fout = 100 to 200 MHz
55
% Fout = 100 to 200 MHz
(VDD/2)
+ 0.2
V
Fout = 100 to 200 MHz
8.3 D.C. Characteristics
VDD = AVDD= 2.5V ±5 %, TA = 0°C to +70°C
PARAMETER
SYM.
SDATA, SCLK Input Low
Voltage
SV_IL
SDATA, SCLK Input High
Voltage
SV_IH
MIN.
TYP.
MAX.
1.0
UNITS
V_dc
2.2
V_dc
TEST CONDITIONS
-6-