W77LE58_07 Datasheet, PDF (74/82 Pages) Winbond – 8-BIT MICROCONTROLLER

W77LE58/W77L058A
Movx Characteristics Using Strech Memory Cycles
PARAMETER
SYMBOL
VARIABLE
CLOCK
MIN.
VARIABLE
CLOCK
MAX.
UNITS STRECH
Data Access ALE Pulse Width
Address Hold After ALE Low
for MOVX write
t_LLHL2
t_LLAX2
1.5 t_CLCL - 5
2.0 t_CLCL - 5
0.5 t_CLCL - 5
nS
t_MCS = 0
t_MCS>0
nS
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold after Read
Data Float after Read
ALE Low to Valid Data In
t_RLRH
2.0 t_CLCL - 5
t_MCS - 10
nS
t_WLWH
2.0 t_CLCL - 5
t_MCS - 10
nS
t_RLDV
2.0 t_CLCL - 20
nS
t_MCS - 20
t_RHDX
0
nS
t_RHDZ
t_CLCL - 5
nS
2.0 t_CLCL - 5
t_LLDV
2.5 t_CLCL - 5
t_MCS + 2 t_CLCL -
nS
40
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS>0
Port 0 Address to Valid Data In
t_AVDV1
3.0 t_CLCL - 20
nS
2.0 t_CLCL - 5
ALE Low to RD or WR Low
t_LLWL
0.5 t_CLCL - 5
1.5 t_CLCL - 5
0.5 t_CLCL + 5
1.5 t_CLCL + 5
nS
Port 0 Address to RD or WR
Low
t_AVWL
t_CLCL - 5
2.0 t_CLCL - 5
nS
Port 2 Address to RD or WR
Low
t_AVWL2
1.5 t_CLCL - 5
2.5 t_CLCL - 5
nS
-5
Data Valid to WR Transition
t_QVWX
1.0 t_CLCL - 5
nS
Data Hold after Write
t_WHQX
t_CLCL - 5
2.0 t_CLCL - 5
nS
RD Low to Address Float
t_RLAZ
0.5 t_CLCL - 5
nS
RD or WR high to ALE high
0
10
t_WHLH
1.0 t_CLCL - 5
1.0 t_CLCL + 5
nS
t_MCS = 0
t_MCS>0
t_MCS = 0
t_MCS > 0
t_MCS = 0
t_MCS > 0
t_MCS = 0
t_MCS > 0
t_MCS = 0
t_MCS > 0
t_MCS = 0
t_MCS > 0
t_MCS = 0
t_MCS > 0
Note: t_MCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of t_MCS for
each selection of the Stretch value.
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