W77LE58_07 Datasheet, PDF (63/82 Pages) Winbond – 8-BIT MICROCONTROLLER

W77LE58/W77L058A
Table 10. Serial Ports Modes
SM1
0
0
1
1
SM0
0
1
0
1
MODE
0
1
2
3
TYPE BAUD CLOCK
Synch.
Asynch.
Asynch.
Asynch.
4 or 12 TCLKS
Timer 1 or 2
32 or 64 TCLKS
Timer 1 or 2
FRAME
SIZE
8 bits
10 bits
11 bits
11 bits
START
BIT
No
1
1
1
STOP
BIT
No
1
1
1
9TH BIT
FUNCTION
None
None
0, 1
0, 1
Framing Error Detection
A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically the frame error is due to noise and contention on the serial communication
line. The W77L058 has the facility to detect such framing errors and set a flag which can be checked
by software.
The Frame Error FE(FE_1) bit is located in SCON.7(SCON1.7). This bit is normally used as SM0 in
the standard 8051 family. However, in the W77L058 it serves a dual function and is called SM0/FE
(SM0_1/FE_1). There are actually two separate flags, one for SM0 and the other for FE. The flag that
is actually accessed as SCON.7(SCON1.7) is determined by SMOD0 (PCON.6) bit. When SMOD0 is
set to 1, then the FE flag is indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is
indicated in SM0/FE.
The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while
reading or writing to FE or FE_1. If FE is set, then any following frames received without any error will
not clear the FE flag. The clearing has to be done by software.
Multiprocessor Communications
Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the W77L058, the
RI flag is set only if the received byte corresponds to the Given or Broadcast address. This hardware
feature eliminates the software overhead required in checking every received address, and greatly
simplifies the software programmer task.
In the multiprocessor communication mode, the address bytes are distinguished from the data bytes
by transmitting the address with the 9th bit set high. When the master processor wants to transmit a
block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All
the slave processors should have their SM2 bit set high when waiting for an address byte. This
ensures that they will be interrupted only by the reception of a address byte. The Automatic address
recognition feature ensures that only the addressed slave will be interrupted. The address comparison
is done in hardware not software.
The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 =
0, the slave will be interrupted on the reception of every single complete frame of data. The
unaddressed slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th
bit is the stop bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is
received and the received byte matches the Given or Broadcast address.
The Master processor can selectively communicate with groups of slaves by using the Given Address.
All the slaves can be addressed together using the Broadcast Address. The addresses for each slave
are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the
SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in
SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in
SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives
the user flexibility to address multiple slaves without changing the slave address in SADDR.
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Publication Release Date: February 1, 2007
Revision A7