W83194R-81 Datasheet, PDF (7/18 Pages) Winbond – 100MHZ CLOCK FOR SIS CHIPSET

W83194R-81
PRELIMINARY
8.0 FUNTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to
assure correct pulse widths. When MODE=0, pins 17, 18, 20 and 21 are inputs (PCI_STOP#),
(CPU_STOP#), (SDRAM_STOP#), (PD#). when MODE=1, these functions are not available. A
particular clock could be enabled as both the 2-wire serial control interface and one of these pins
indicate that it should be enabled.
The W83194R-81 may be disabled in the low state according to the following table in order to reduce
power consumption. All clocks are stopped in the low state, but maintain a valid high period on
transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
MODE PIN-POWER MANAGEMENT INPUT
MODE(Pin2)
0 (Input)
1 (Output)
Pin17
CPU_STOP#
SDRAM11
Pin18
PCI_STOP#
SDRAM10
Pin20
SDRAM_STOP#
SDRAM9
Pin21
PD#
SDRAM8
PD# CPU_STOP# PCI_STOP#
0
X
X
1
X
X
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
SDRAM
_STOP#
X
X
1
0
1
0
1
0
1
0
PCI [0:4]
Low
Running
Running
Running
Low
Low
Running
Running
Low
Low
SDRAM
[0:12]
Low
Running
Running
Running
Running
Low
Running
Low
Running
Low
CPU[1:2]
Low
Running
Running
Running
Running
Running
Low
Low
Low
Low
XTAL &
VCOs
Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Publication Release Date: Dec. 1998
-7-
Revision 0.20