W83194R-81 Datasheet, PDF (11/18 Pages) Winbond – 100MHZ CLOCK FOR SIS CHIPSET

W83194R-81
PRELIMINARY
8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
- Reserved
6
1
25 24/14MHz(Active / Inactive)
5
1
26 48MHz(Active / Inactive)
4
1
15 SDRAM12 (Active / Inactive)
3
1
17 SDRAM11 (Active / Inactive)
2
1
18 SDRAM10 (Active / Inactive)
1
1
20 SDRAM9 (Active / Inactive)
0
1
21 SDRAM8 (Active / Inactive)
8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
- Reserved
6
-
- Latched FS2#
5
1
- Reserved
4
1
47 IOAPIC (Active / Inactive)
3
-
- Latched SD_SEL
2
1
44 REF2 (Active / Inactive)
1
1
46 REF1 (Active / Inactive)
0
1
2 REF0 (Active / Inactive)
8.3.7 Register 6: Winbond Chip ID Register (Read Only)
Bit @PowerUp Pin
7
0
- Winbond Chip ID
6
1
- Winbond Chip ID
5
0
- Winbond Chip ID
4
1
- Winbond Chip ID
3
0
- Winbond Chip ID
2
1
- Winbond Chip ID
1
0
- Winbond Chip ID
0
0
- Winbond Chip ID
Description
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Publication Release Date: Dec. 1998
Revision 0.20