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W83194R-81 Datasheet, PDF (10/18 Pages) Winbond – 100MHZ CLOCK FOR SIS CHIPSET
W83194R-81
PRELIMINARY
8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
- Reserved
6
1
- Reserved
5
1
- Reserved
4
1
- Reserved
3
1
40 CPUCLK2 (Active / Inactive)
2
1
41 CPUCLK1 (Active / Inactive)
1
1
43 CPUCLK0 (Active / Inactive)
0
-
- Latched FS0#
8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
-
- Latched FS1#
6
1
7 PCICLK_F (Active / Inactive)
5
1
- Reserved
4
1
13 PCICLK4 (Active / Inactive)
3
1
12 PCICLK3 (Active / Inactive)
2
1
11 PCICLK2 (Active / Inactive)
1
1
10 PCICLK1 (Active / Inactive)
0
1
8 PCICLK0 (Active / Inactive)
8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7
1
28 SDRAM7 (Active / Inactive)
6
1
29 SDRAM6 (Active / Inactive)
5
1
31 SDRAM5 (Active / Inactive)
4
1
32 SDRAM4 (Active / Inactive)
3
1
34 SDRAM3 (Active / Inactive)
2
1
35 SDRAM2 (Active / Inactive)
1
1
37 SDRAM1 (Active / Inactive)
0
1
38 SDRAM0 (Active / Inactive)
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Publication Release Date: Dec. 1998
Revision 0.20