W39V040A Datasheet, PDF (7/34 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V040A
Continued
100
101
110
111
FFDF, FFFFh: FFD8, 0000h
FFD7, FFFFh: FFD0, 0000h
FFCF, FFFFh: FFC8, 0000h
FFC7, FFFFh: FFC0, 0000h
Table of Operating Modes
Operating Mode Selection - Programmer Mode
MODE
Read
Write
Standby
Write Inhibit
Output Disable
#OE
VIL
VIH
X
VIL
X
VIH
#WE
VIH
VIL
X
X
VIH
X
PINS
#RESET ADDRESS
VIH
AIN
VIH
AIN
VIL
X
VIH
X
VIH
X
VIH
X
DQ.
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
Standard LPC Memory Cycle Definition
FIELD
Start
Cycle Type & Dir
TAR
Addr.
Sync.
Data
NO. OF
CLOCKS
DESCRIPTION
1
"0000b" appears on LPC bus to indicate the initial
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
2
Turned Around Time
Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
8
The addresses transfer most significant nibble first and least significant nibble
last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means Short
N
Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble first
2
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)
Publication Release Date: December 19, 2002
-7-
Revision A2