W39V040A Datasheet, PDF (17/34 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V040A
AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
Read Cycle Time
Row/Column Address Set Up Time
Row/Column Address Hold Time
Address Access Time
Output Enable Access Time
#OE Low to Act Output
#OE High to High-Z Output
Output Hold from Address Change
SYMBOL
TRC
TAS
TAH
TAA
TOE
TOLZ
TOHZ
TOH
W39V040A
MIN.
MAX.
300
-
50
-
50
-
-
175
-
75
0
-
-
35
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle Timing Parameters
PARAMETER
Reset Time
Address Setup Time
Address Hold Time
R/#C to Write Enable High Time
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
#OE Hold Time
Byte Programming Time
Sector/Page Erase Cycle Time
Chip Erase Cycle Time
SYMBOL
TRST
TAS
TAH
TCWH
TWP
TWPH
TDS
TDH
TOEH
TBP
TPEC
TEC
MIN.
1
50
50
50
100
100
50
50
0
-
-
-
TYP.
-
-
-
-
-
-
-
-
-
35
20
75
MAX.
-
-
-
-
-
-
-
-
-
50
25
100
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
PARAMETER
SYMBOL
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
TOEP
TOET
W39V040A
MIN.
MAX.
-
40
-
40
UNIT
µS
nS
nS
nS
nS
nS
nS
nS
nS
µS
mS
mS
UNIT
nS
nS
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Publication Release Date: December 19, 2002
Revision A2