W39V040A Datasheet, PDF (21/34 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Diagram
A[10:0]
(Internal A[18:0])
DQ[7:0]
Six-byte code for 3.3V-only software chip erase
5555
AA
2AAA
5555
5555
2AAA
5555
55
80
AA
55
10
R/#C
#OE
#WE
TWP
TWPH
SB0
SB1
SB2
SB3
SB4
SB5
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
T EC
Internal Erasure Starts
Sector/Page Erase Timing Diagram
A[10:0]
(Internal A[18:0])
DQ[7:0]
Six-byte code for 3.3V-only
Sector/Page Erase
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
SA/PA
30/50
R/#C
#OE
TWP
TEC
#WE
TWPH
SB0
SB1
SB2
SB3
SB4
SB5
Internal Erase starts
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
SA = Sector Address and PA = Page Address, Please ref. to the "Table of Command Definition"
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Publication Release Date: December 19, 2002
Revision A2