W9712G6JB Datasheet, PDF (65/86 Pages) Winbond – 2M × 4 BANKS × 16 BIT DDR2 SDRAM

W9712G6JB
9.12 AC Input Test Conditions
(0℃ ≤ TCASE ≤ 85℃ for -18/-25/-3, VDD, -40℃ ≤ TCASE ≤ 95℃ for 25I/25A, VDD, VDDQ = 1.8V ± 0.1V)
CONDITION
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
SYMBOL
VREF
VSWING(MAX)
SLEW
VALUE
0.5 x VDDQ
1.0
1.0
UNIT
V
V
V/nS
NOTES
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(ac) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the
range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
9.13 Differential Input/Output AC Logic Levels
(0℃ ≤ TCASE ≤ 85℃ for -18/-25/-3, VDD, -40℃ ≤ TCASE ≤ 95℃ for 25I/25A, VDD, VDDQ = 1.8V ± 0.1V)
PARAMETER
SYM.
MIN.
MAX.
UNIT NOTES
AC differential input voltage
VID (ac)
0.5
VDDQ + 0.6
V
1
AC differential cross point input voltage
VIX (ac) 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175
V
2
AC differential cross point output voltage VOX (ac) 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125 V
3
Notes:
1. VID (ac) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such
as CLK, LDQS or UDQS) and VCP is the complementary input signal (such as CLK , LDQS or UDQS ). The minimum
value is equal to VIH (ac) - VIL (ac).
2. The typical value of VIX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VIX (ac) is expected to track
variations in VDDQ. VIX (ac) indicates the voltage at which differential input signals must cross.
3. The typical value of VOX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (ac) is expected to
track variations in VDDQ. VOX (ac) indicates the voltage at which differential output signals must cross.
VSWING(MAX)
△TF
VREF - VIL(ac) max
Falling Slew =
△TF
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
△TR
VIH(ac) min - VREF
Rising Slew =
△TR
VDDQ
VTR
Crossing point
VID
VCP
VIX or VOX
VSSQ
Figure 28—AC input test signal and Differential signal levels waveform
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Publication Release Date: Mar. 15, 2010
Revision A01