W9712G6JB Datasheet, PDF (5/86 Pages) Winbond – 2M × 4 BANKS × 16 BIT DDR2 SDRAM

W9712G6JB
3. KEY PARAMETERS
SYM.
SPEED GRADE
Bin(CL-tRCD-tRP)
Part Number Extension
@CL = 7
@CL = 6
tCK(avg) Average clock period
@CL = 5
@CL = 4
@CL = 3
tRCD
tRP
tRC
tRAS
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating current
Operation current (Single bank)
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current
Operating bank interleave read current
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
DDR2-1066
7-7-7
-18
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
7.5 nS
3.75 nS
7.5 nS
−
−
13.125 nS
13.125 nS
53.125 nS
40 nS
80 mA
95 mA
165 mA
160 mA
95 mA
3 mA
195 mA
DDR2-800
5-5-5/6-6-6
-25/25I/25A
−
−
2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
12.5 nS
52.5 nS
40 nS
75 mA
90 mA
140 mA
135 mA
85 mA
3 mA
170 mA
DDR2-667
5-5-5
-3
−
−
−
−
3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
15 nS
55 nS
40 nS
70 mA
85 mA
130 mA
125 mA
80 mA
3 mA
160 mA
Publication Release Date: Mar. 15, 2010
-5-
Revision A01