W9712G6JB Datasheet, PDF (4/86 Pages) Winbond – 2M × 4 BANKS × 16 BIT DDR2 SDRAM

W9712G6JB
1. GENERAL DESCRIPTION
The W9712G6JB is a 128M bits DDR2 SDRAM, organized as 2,097,152 words × 4 banks × 16 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W9712G6JB is sorted into the following speed grades: -18, -25, 25I, 25A and -3. The -18
is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I/25A are compliant to the DDR2-800
(5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade and 25A automotive grade which is
guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5)
specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
z Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
z Double Data Rate architecture: two data transfers per clock cycle
z CAS Latency: 3, 4, 5, 6 and 7
z Burst Length: 4 and 8
z Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
z Edge-aligned with Read data and center-aligned with Write data
z DLL aligns DQ and DQS transitions with clock
z Differential clock inputs (CLK and CLK )
z Data masks (DM) for write data.
z Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
z Posted CAS programmable additive latency supported to make command and data bus efficiency
z Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
z Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
z Auto-precharge operation for read and write bursts
z Auto Refresh and Self Refresh modes
z Precharged Power Down and Active Power Down
z Write Data Mask
z Write Latency = Read Latency - 1 (WL = RL - 1)
z Interface: SSTL_18
z Packaged in WBGA 84 Ball (8X12.5 mm²), using Lead free materials with RoHS compliant
Publication Release Date: Mar. 15, 2010
-4-
Revision A01