W9712G6JB Datasheet, PDF (22/86 Pages) Winbond – 2M × 4 BANKS × 16 BIT DDR2 SDRAM

W9712G6JB
commands must be registered on each positive clock edge during the Self Refresh exit interval tXSNR.
ODT should be turned off during tXSRD.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2
SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh
mode.
7.3.9 Refresh Command
( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A11 = Don’t Care)
Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles
at an average periodic interval of tREFI (max.).
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle)
state. A delay between the auto refresh command (REF) and the next activate command or
subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command
and the next Refresh command is 9 x tREFI.
T0
T1
T2
T3
Tm
CLK/CLK
CKE
"HIGH"
≥ tRP
≥ tRFC
Tn
Tn + 1
≥ tRFC
CMD Precharge
NOP
NOP
REF
REF
NOP
ANY
Figure 13—Refresh command
- 22 -
Publication Release Date: Mar. 15, 2010
Revision A01