W77C58 Datasheet, PDF (65/71 Pages) Winbond – 8 BIT MICROCONTROLLER

Preliminary W77C58
MOVX Characteristics Using Strech Memory Cycles
PARAMETER
SYM.
VARIABLE
CLOCK
MIN.
VARIABLE UNITS STRECH
CLOCK
MAX.
Data Access ALE Pulse Width
Address Hold After ALE Low for
MOVX Write
t_LLHL2
tLLAX2
1.5 tCLCL - 5
2.0 tCLCL - 5
0.5 tCLCL - 5
nS
tMCS = 0
tMCS > 0
nS
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold after Read
Data Float after Read
ALE Low to Valid Data In
tRLRH
2.0 tCLCL - 5
nS
tMCS - 10
tWLWH
2.0 tCLCL - 5
nS
tMCS - 10
t_RLDV
2.0 tCLCL - 20
nS
tMCS - 20
t_RHDX
0
nS
t_RHDZ
tCLCL - 5
nS
2.0 tCLCL - 5
tLLDV
2.5 tCLCL - 5
nS
tMCS + 2tCLCL
- 40
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
Port 0 Address to Valid Data In
Port 2 Address to Valid Data In
ALE Low to RD or WR Low
Port 0 Address to RD or WR Low
Port 2 Address to RD or WR Low
Data Valid to WR Transition
Data Hold after Write
RD Low to Address Float
t_AVDV1
3.0 tCLCL - 20
nS
2.0tCLCL - 5
t_AVDV2
3.5 tCLCL - 20
nS
2.5 tCLCL - 5
tLLWL
0.5 tCLCL - 5
0.5 tCLCL + 5
nS
1.5 tCLCL - 5 1.5 tCLCL + 5
tAVWL
tCLCL - 5
nS
2.0 tCLCL - 5
t_AVWL2
1.5 tCLCL - 5
nS
2.5 tCLCL - 5
t_QVWX
-5
nS
1.0 tCLCL - 5
tWHQX
tCLCL - 5
nS
2.0 tCLCL - 5
t_RLAZ
0.5 tCLCL - 5
nS
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
RD or WR High to ALE High
t_WHLH
0
10
nS
1.0 tCLCL - 5 1.0 tCLCL + 5
tMCS = 0
tMCS > 0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of t_MCS for each
selection of the Stretch value.
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Publication Release Date: September 1999
Revision A1