W77C58 Datasheet, PDF (40/71 Pages) Winbond – 8 BIT MICROCONTROLLER

Preliminary W77C58
POWER MANAGEMENT
The W77C58 has several features that help the user to modify the power consumption of the device.
The power saving features are basically the POWER DOWN mode, ECONOMY mode and the IDLE
mode of operation.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets
the idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the
Idle mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial
port blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the
Program Status Word, the Accumulator and the other registers hold their contents. The ALE and
PSEN pins are held high during the Idle state. The port pins hold the logical states they had at the
time Idle was activated. The Idle mode can be terminated in two ways. Since the interrupt controller is
still active, the activation of any enabled interrupt can wake up the processor. This will automatically
clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine (ISR) will be executed.
After the ISR, execution of the program will continue from the instruction which put the device into
Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either by
applying a high on the external RST pin, a Power on/fail reset condition or a Watchdog timer reset.
The external reset pin has to be held high for at least two machine cycles I.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the W77C58 is exiting from an Idle mode with a reset, the instruction following the one which
put the device into Idle mode is not executed. So there is no danger of unexpected writes.
Economy Mode
The power consumption of microcontroller relates to operating frequency. The W77C58 offers a
Economy mode to reduce the internal clock rate dynamically without external components. By
default, one machine cycle needs 4 clocks. In Economy mode, software can select 4, 64 or 1024
clocks per machine cycle. It keeps the CPU operating at a acceptable speed but eliminates the power
consumption. In the Idle mode, the clock of the core logic is stopped, b+ut all clocked peripherals
such as watchdog timer are still running at a rate of clock/4. In the Economy mode, all clocked
peripherals run at the same reduced clocks rate as in core logic. So the Economy mode may provide
a lower power consumption than idle mode.
Software invokes the Economy mode by setting the appropriate bits in the SFRs. Setting the bits
CD0(PMR.6),CD1(PMR.7) decides the instruction cycle rate as below:
CD1 CD0 clocks/machine cycle
00
Reserved
01
4 (default)
10
64
11
1024
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