W24L11 Datasheet, PDF (6/11 Pages) Winbond – 128K X 8 High Speed CMOS Static RAM

Preliminary W24L11
Timing Waveforms, continued
Write Cycle 1
Address
OE
CS1
CS2
WE
DOUT
DIN
TWC
TCW
TWR
TAW
TAS
TOHZ _{(1, 4)}
TWP
TDW
TDH
Write Cycle 2
(OE = VIL Fixed)
Address
CS1
T WC
TCW
TWR
CS2
WE
D _OUT
DIN
TAW
TAS
T WP
TOH
TWHZ
(1, 4)
TOW
(2)
(3)
TDW
TDH
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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