W24L010A Datasheet, PDF (6/9 Pages) Winbond – 128K X 8 High Speed CMOS Static RAM

W24L010A
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
Address
OE
CS1
CS2
WE
D OUT
D IN
T WC
TWR1
TCW1
TAS
T_OHZ
TCW2
TAW
TWP
(1, 4)
TWR2
T_DW
TDH
Write Cycle 2
(OE = VIL Fixed)
Address
CS1
CS2
WE
D OUT
D IN
TWC
T CW1
TWR1
TCW2
TAW
TWR2
TAS
TWP
TOH
TWHZ (1, 4)
TOW
(2)
(3)
TDW
TDH
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. Dout provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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