W24L010A Datasheet, PDF (5/9 Pages) Winbond – 128K X 8 High Speed CMOS Static RAM

TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
DOUT
TRC
TAA
TOH
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
D_OUT
Read Cycle 3
(Output Enable Controlled)
Address
OE
CS1
CS2
DOUT
TACS1
TACS2
TCLZ1
TCLZ2
TRC
T_AA
TAOE
TOLZ
TACS1
TCLZ1
TACS2
TCLZ2
W24L010A
TOH
TCHZ1
TCHZ2
TOH
TCHZ1
TCHZ2 ^TOHZ
Publication Release Date: September 1999
-5-
Revision A2