W25Q80DVSNIG-TR Datasheet, PDF (53/71 Pages) Winbond – 3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q80DV
Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more
data bytes to be sequentially read from one of the four security registers. The instruction is initiated by
driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-
A0) and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge
of the CLK pin. After the address is received, the data byte of the addressed memory location will be
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address
is automatically incremented to the next byte address after each byte of data is shifted out. Once the
byte address reaches the last byte of the register (byte FFh), It will reset to 00h, the first byte of the
register, and continue to increment. The instruction is completed by driving /CS high. The Read Security
Register instruction sequence is shown in figure 37. If a Read Security Register instruction is issued
while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not
have any effects on the current cycle. The Read Security Register instruction allows clock rates from
D.C. to a maximum of FR (see AC Electrical Characteristics).
ADDRESS
Security Register #1
Security Register #2
Security Register #3
A23-16
00h
00h
00h
A15-12
0001
0010
0011
A11-8
0000
0000
0000
A7-0
Byte Address
Byte Address
Byte Address
Instruction (48h)
Figure 37. Read Security Registers Instruction Sequence
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Publication Release Date:July 21, 2015
Prelimry-Revision G