W25Q80DVSNIG-TR Datasheet, PDF (31/71 Pages) Winbond – 3V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q80DV
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable
bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Byte 1 Byte 2
Figure 14a. Fast Read Quad I/O Instruction Sequence (M[7:0] =FFh)
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Publication Release Date:July 21, 2015
Prelimry-Revision G