W78LE365_07 Datasheet, PDF (5/42 Pages) Winbond – 8-BIT MICROCONTROLLER

W78LE365/W78L365A
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
I ^{external ROM. The ROM address and data will not be presented on the bus if}
the EA pin is high.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
P3.0−P3.7
P4.0−P4.7
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
O H _{Port 0 address/data bus. When internal ROM access is performed, no PSEN}
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
O H separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
IL
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
I GROUND: ground potential.
I POWER SUPPLY: Supply voltage for operation.
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
and P2.7 also provide the alternate function REBOOT which is H/W reboot
from LD flash.
I/O H PORT 3: Function is the same as that of the standard 8052.
PORT 4: A bi-directional I/O. The P4.3 also provide the alternate function
I/O H
REBOOT which is H/W reboot from LD flash.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: January 10, 2007
-5-
Revision A7