W78LE365_07 Datasheet, PDF (19/42 Pages) Winbond – 8-BIT MICROCONTROLLER

W78LE365/W78L365A
5.9 In-System Programming (ISP) Mode
The W78L365A equips one 64K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78L365A allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register. The CHPCON is read-only by default, software must write two specific values 87H,
then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute. The W78L365A achieves all in-system programming operations including enter/exit ISP
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device
needs proper time to complete the ISP operations before awaken from idle mode, software may use
timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
to reset the CPU. The software reset serves as a external reset. This in-system programming feature
makes the job easy and efficient in which the application needs to update firmware frequently. In some
applications, the in-system programming feature make it possible to easily update the system
firmware without opening the chassis.
SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address.
SFRFD: The programming data for on-chip ROM in programming mode.
SFRCN: The control byte of on-chip ROM programming mode.
SFRCN (C7)
BIT
7
6
5
4
3, 2, 1, 0
NAME
FUNCTION
-
Reserve.
On-chip ROM bank select for in-system programming.
WFWIN = 0: 64K bytes ROM bank is selected as destination for re-programming.
= 1: 4K bytes ROM bank is selected as destination for re-programming.
OEN ROM output enable.
CEN ROM chip enable.
CTRL[3:0] The flash control signals
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Publication Release Date: January 10, 2007
Revision A7