W78LE365_07 Datasheet, PDF (29/42 Pages) Winbond – 8-BIT MICROCONTROLLER

W78LE365/W78L365A
8. TIMING WAVEFORMS
8.1 Program Fetch Cycle
XTAL1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
ALE
T_APL
T_ALW
PSEN
PORT 2
T_PSW
T_AAS
T_AAH
T_PDA
T_PDH, T_PDZ
PORT 0
Code A0-A7
Data ^A0-A7
Code A0-A7
Data A0-A7
PARAMETER
SYMBOL
MIN.
TYP.
Address Valid to ALE Low
TAAS
1 TCP-∆
-
Address Hold from ALE Low
TAAH
1 TCP-∆
-
ALE Low to PSEN Low
TAPL
1 TCP-∆
-
PSEN Low to Data Valid
TPDA
-
-
Data Hold after PSEN High
TPDH
0
-
Data Float after PSEN High
TPDZ
0
-
ALE Pulse Width
TALW
2 TCP-∆ 2 TCP
PSEN Pulse Width
TPSW
3 TCP-∆ 3 TCP
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
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Publication Release Date: January 10, 2007
Revision A7