W949D6CB Datasheet, PDF (49/60 Pages) Winbond – 512Mb Mobile LPDDR

W949D6CB / W949D2CB
PARAMETER
Operating one
bank active-
precharge
current
Precharge
power-down
standby current
Precharge
power-down
standby current
with clock stop
Precharge non
power-down
standby current
Precharge non
power-down
standby current
with clock stop
Active power-
down standby
current
Active power-
down standby
current with
clock stop
Active non
power-down
standby current
Active non
power-down
standby current
with clock stop
Operating burst
read current
Operating burst
write current
Auto-Refresh
Current
SYMBOL
IDD0
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4R
IDD4W
IDD5
TEST CONDITION
512Mb Mobile LPDDR
(X32)
- 5 - 6 - 75 UNIT
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid _{40 38 35 mA}
commands; address inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
Low
power
0.6
0.6
0.6
mA
Normal
power
0.8
0.8
0.8
Low
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = power ^{0.6 0.6 0.6}
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
mA
Normal
power
0.8
0.8
0.8
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus
inputs are STABLE
10 10 10 mA
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
33
3 mA
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and ₃
3
3 mA
control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; ₃
3
3 mA
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and _{25 25 25 mA}
control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; _{15 15 15 mA}
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts;
IOUT = 0 mA; address inputs are SWITCHING; 50% data change each
burst transfer
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change
each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data bus inputs are
STABLE
75 70 70 mA
55 50 50 mA
75 75 75 mA
Deep Power-
Down current
IDD8(4)
Address and control inputs are STABLE; data bus inputs are STABLE
10 10 10 _uA
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is 1V/ns.
3. Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ;HIGH is defined as VIN ≥ 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- Address and command: inputs changing between HIGH and LOW once per two clock cycles;
- Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
4. IDD8 are typical value at 25℃.
- 49 -
Publication Release Date: Sep, 21, 2011
Revision A01-007