W949D6CB Datasheet, PDF (48/60 Pages) Winbond – 512Mb Mobile LPDDR

W949D6CB / W949D2CB
8.4 IDD Specification Parameters and Test Conditions
8.4.1 IDD Specification Parameters and Test Conditions
512Mb Mobile LPDDR
(X16)
PARAMETER SYMBOL
TEST CONDITION
- 5 - 6 - 75 UNIT
Operating one
bank active-
precharge
current
IDD0
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are
40 38 35 mA
STABLE
Precharge
power-down
standby current
IDD2P
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
Low
power
0.6
0.6
0.6
mA
Normal
power
0.8
0.8
0.8
Precharge
power-down
standby current
with clock stop
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK =
Low
power
0.6
0.6
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
Normal
power
0.8
0.8
0.6
0.8
mA
Precharge non
power-down
standby current
IDD2N
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
10 10 10 mA
Precharge non
power-down
standby current
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
3
address and control inputs are SWITCHING; data bus inputs are STABLE
3
with clock stop
3 mA
Active power-
down standby
current
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;address and ₃
3
control inputs are SWITCHING; data bus inputs are STABLE
3 mA
Active power-
down standby
current with
IDD3PS
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; ₃
address and control inputs are SWITCHING; data bus inputs are STABLE
3
clock stop
3 mA
Active non
power-down
standby current
IDD3N
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address
and control inputs are SWITCHING; data bus inputs are STABLE
25 25 25 mA
Active non
power-down
standby current
IDD3NS
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; _{15 15}
address and control inputs are SWITCHING; data bus inputs are STABLE
15
mA
with clock stop
Operating burst
read current
IDD4R
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts;
IOUT = 0 mA; address inputs are SWITCHING; 50% data change each
burst transfer
75 70 70 mA
Operating burst
write current
IDD4W
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change each burst
transfer
55 50 50 mA
Auto-Refresh
Current
IDD5
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH; address and
control inputs are SWITCHING; data bus inputs are STABLE
75
75
75
mA
Deep Power-
Down current
IDD8(4)
Address and control inputs are STABLE; data bus inputs are STABLE
10 10 10 uA
- 48 -
Publication Release Date: Sep, 21, 2011
Revision A01-007