W49L201 Datasheet, PDF (4/23 Pages) Winbond – 256K X 8 CMOS FLASH MEMORY

Preliminary W49L201
during this operation. The entire memory array will be erased to FF(hex) by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function will erase all the sectors except the boot mode.
Sector Erase Operation
The three sectors, main memory and two parameters blocks, can be erased individually by initiating a
six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle
while the 30(hex) data input command is latched at the rising edge of WE. After the command
loading cycle, the device enters the internal sector erase mode, which is automatically timed and will
be completed in a fast 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
When the boot block lockout feature is inactivated, the boot block and the main memory block will be
erased together. Once the boot block is locked, only the main memory block will be erased by the
execution of sector erase operation.
Program Operation
The W49L201 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50 µS max. -
TBC) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49L201 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
1.8V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
10 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49L201 includes a data polling feature to indicate the end of a program or erase cycle. When
the W49L201 is in the internal program or erase cycle, any attempt to read DQ7 of the last word
loaded will receive the complement of the true data. Once the program or erase cycle is completed,
DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become
logical "1" or true data when the erase cycle has been completed.
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