W49L201 Datasheet, PDF (17/23 Pages) Winbond – 256K X 8 CMOS FLASH MEMORY

W49L201
Timing Waveforms, continued
CE Controlled Command Write Cycle Timing Diagram
Address A16-0
CE
OE
WE
DQ15-0
TAS
TOES
High Z
TAH
TCP
TCPH
TOEH
TDS
Data Valid
TDH
Program Cycle Timing Diagram
Address A16-0
DQ15-0
CE *
5555
2AAA
Word Program Cycle
5555
Address
AA
55
A0
Data-In
OE *
T WPH
TBC
TWP
WE
Word 0
Word 1
Word 2
Word 3
Internal Write Start
*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the
command sequence. If read command is asserted during the command
sequence, then the device will return to read mode(abort write).
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Publication Release Date: May 2000
Revision A1