W9812G6JB Datasheet, PDF (39/42 Pages) Winbond – 2M x 4 BANKS 꼌 16 BITS SDRAM

W9812G6JB
11.21 CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
D1
D2
3
4
5
6
7
D3
D5
D6
DQM MASK
( 1)
CKE MASK
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
D1
D2
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
D1
D2
3
4
5
6
7
D3
D5
D6
DQM MASK
( 2)
CKE MASK
3
4
5
6
7
D3
D4
CKE MASK
( 3)
D5
D6
- 39 -
Publication Release Date: Oct. 15, 2013
Revision A02