W9812G6JB Datasheet, PDF (16/42 Pages) Winbond – 2M x 4 BANKS 꼌 16 BITS SDRAM

W9812G6JB
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum
values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
5. Power up sequence is further described in the “Functional Description” section.
6. AC test load diagram.
output
Z = 50 ohms
1.4 V
50 ohms
30pF
AC TEST LOAD
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output
level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter.
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
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Publication Release Date: Oct. 15, 2013
Revision A02