W78C354 Datasheet, PDF (31/44 Pages) Winbond – MONITOR MICROCONTROLLER

W78C354
VSPS
HSPS
DUMMYEN
ENVS
VIN
HIN
AD[7:0]
VDISHC
Polarity
VREST
Detect & _HREST
Restoration
0
VSEP
Sync
1
Separator
H/V
Frequency
Counter
H/V Dummy
Sync
Generator
VDUMMY
HDUMMY
H-Clamp
Generator
SOA
Generator
0
0
1
1
0
0
1
1
VOUT
HOUT
H - Clamp
SOA
Figure 11. Sync processor
M-1. Polarity Detector
The H/V polarity is detected automatically and can be read from SFR STATUS. The polarity of the
H/V input signals is then restored (they signals become HREST/VREST) for internal processing and
output to HOUT/VOUT to drive the deflection circuit.
Maximum sync width to HIN pin: (1/FCLOCK ) × 2¹⁴
Maximum sync width to VIN pin: (1/FCLOCK ) × 2¹⁴
FCLOCK
16 MHz
18.432 MHz
20 MHz
Max. sync width for HIN
Max. sync width for VIN
1024 µS
1024 µS
888 µS
888 µS
819 µS
819 µS
M-2. Sync Separator
Vsync is separated from the composite sync automatically, without any additional software
programming. Figure 12 shows the waveforms of VOUT that result from a composite or non-composite
Hsync input.
If ENVS = 1, the limitations on the Vsync signal are:
VIN pulse width must be larger than Wvmin = [(1/FCLOCK)¡Ñ128.5] ± 1/(2 × FCLOCK₎
VOUT is delayed from VIN signal by Tdelay = [(1/FCLOCK)¡Ñ128.5] ± 1/(2 × FCLOCK₎
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Publication Release Date: October 1996
Revision A1