W78C354 Datasheet, PDF (20/44 Pages) Winbond – MONITOR MICROCONTROLLER

W78C354
G-1.5 STA (SIO1 Start Flag)
When STA is "1," the SIO port will enter the master mode. After the SIO1 port checks the status of
the I²C bus, it will generate a start condition if the bus is free. If the bus is not free, the SIO1 port will
wait for a stop condition and then generate a start condition after a delay.
If the bit STA is set while SIO1 is already in master mode and one or more bytes are to be
transmitted or received, SIO1 will transmit a repeated start condition. The bit STA may also be set
when SIO1 is an addressed slave.
When STA is "0," no start condition or repeated start condition will be generated.
G-1.6 STO (SIO1 Stop Flag)
When STO is "1," the SIO1 port is in the master mode and a stop condition is transmitted to the I²C
bus. When the stop condition is detected on the bus, the SIO1 port will clear STO. In the slave mode,
STO may be set to recover from an error condition. In this case, no stop condition exists the I²C bus,
but the SIO1 port behaves as if a stop condition has been received and switches to the defined "not
addressed" slave receiver mode. STO is automatically cleared by hardware.
G-1.7 SI (SIO1 Serial Interrupt Flag)
When SI is "1," if the bits EA and ES1 (in the IE register) are also set, then once a serial interrupt is
requested, SI will automatically be set by hardware. The only state that does not cause SI to be set is
state F8H, which indicates that no relevant state information is available.
When the bit SI is "1," the low period of the serial clock on the SCL pin is extended, and the serial
transfer is suspended. SI must be reset by software.
When SI is "0," no serial interrupt is requested, so there is no extension of the serial clock on the SCL
pin.
G-1.8 AA (SIO1 Assert Acknowledge Flag)
If AA is "1," an acknowledge signal (low level to the SDA pin) will be generated during the
acknowledge clock pulse on the SCL pin when:
(1) The address owning the slave has been received.
(2) A data byte has been received while the SIO1 port is in the master receiver mode.
(3) A data byte has been received while the SIO1 port is in the addressed slave receiver mode.
If the bit AA is "0," a not acknowledge signal (high level to the SDA pin) will be generated during the
acknowledge clock pulse on the SCL pin when:
(1) A data byte has been received while the SIO1 port is in the master receiver mode
(2) A data byte has been received while the SIO1 port is in the addressed slave receiver mode.
G-1.9 CR0, CR1 and CR2 (SIO1 Clock Rate Bits)
When the SIO1 port is in master mode, these three bits will determine the serial clock frequency (see
the table below). These bits are unimportant when SIO1 is in slave mode. In slave mode, the SIO1
port will automatically synchronize with any clock frequency up to 100 KHz on the I²C bus.
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