W78C354 Datasheet, PDF (28/44 Pages) Winbond – MONITOR MICROCONTROLLER

W78C354
W78C354
8/12bit SDAC
Low-pass filter
R
C
V OUTPUT
Figure 8. SDAC application circuit (where T = RC, VOUTPUT = VCC × n/255, if T >> TPWM)
When bit ENM0 of SFR CONTREG2 is set to high, SDAC0 will output PWM in one frame and then
keep low for the next frame. Thus SDAC0 can be used for H moire cancellation. SDAC1 can also be
configured with the same operation for V moire cancellation by setting bit ENM1. The application
circuit is shown below.
SDAC0
(H-moire)
SDACx
(H-phase)
H-phase
Control
Circuit
Figure 9. Moire application circuit
L-1.2 Two-channel 12-bit PWM/BRM Static DAC
The two 12-bit PWM/BRM outputs (BSDAC0,1) are composed of an 8-bit PWM and a 4-bit BRM (bit
rate multiplier). The value of the 4-bit BRMs (SFRs SBRM0, 1) determine to which positions one
clock pulse will be added in every 16 PWM outputs of 12-bit PWM/BRM static DAC0,1. When the
"MOV BSDACn, #value" or "MOV SBRMn, #value" instruction is executed, the related output pin will
output the PWM waveform needed by the user. The 12-bit PWM/BRM frequency is the same as that
of the 8-bit PWM output.
VALUE OF SBRM0 OR SBRM1
(BIT3 BIT2 BIT1 BIT0)
ONE CLOCK PLUSE INCREMENTED IN THE N-TH
OUTPUT EVERY 16 PWM OUTPUTS
0000
None
0001
n=8
0010
n = 4, 12
0100
n = 2, 6, 10, 14
1000
n = 1, 3, 5, 7, 9, 11, 13, 15
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