W78C354 Datasheet, PDF (23/44 Pages) Winbond – MONITOR MICROCONTROLLER

W78C354
H-1. Interrupt at Vector Address 0013H
The interrupt at vector address 0013H is driven by another seven different sources, which are a high-
to-low transition on the DSCL pin of the DDC port, the A/D converter, the auto-reload timer, the SOA
output, Vsync frequencg event, the parabola interrupt generator, and DDC1 in the DDC port. These
sources are described below.
(1) DSCLINT:
Interrupt generated when DSCL-pin changes from high to low and stays high for 12 clock periods.
Once DDCLINT interrupt is received, the programmer should disable DDC1 port by writing "0" to the
bit ENDDC1 of SFR CONTREG1.
DSCL low
16 MHz
750 nS
18.432 MHz
651 nS
20 MHz
600 nS
(2) ADCINT:
Refer to section K for a description of the ADC.
(3) TIMEOUT:
Refer to section I for a description of the auto-reload timer.
(4) SOAINT:
When an SOA condition occurs, SOAINT will interrupt the CPU to perform the necessary operations.
Refer to section M-6 for a description of the SOA function.
(5) VEVENT:
When the V retrace signal is detected or the V-frequency counter overflows, which means that the
Vsync frequency is so low that it is out of range, the W78C354 will generate the VEVENT interrupt. In
the interrupt service routine, the programmer can check bit 3 (NOV) of SFR STATUS to determine
whether the V frequency is out of range. If NOV = 1, the software should go to DPMS process. If NOV
= 0, the software can read the HFCOUNT and VFCOUNT registers, and the bits HP and VP of
STATUS will determine the preset mode of the incoming frequency. Refer to section M for a
description of the sync processor.
(6) PARAINT:
The parabola interrupt generator is used to generate interrupts to the W78C354 for loading the
parabola waveform data to dynamic DACs. The software should calculate the value of the PARAH
and PARAL registers by (Vcount × 16) ÷ section number. Refer to section J for a description of the
parabola interrupt generator.
(7) DDC1INT:
Refer to section G-2 for a description of the DDC1 operation.
Programmer must read SFR INTVECT (bits 0−6) to determine the source of the interrupt request.
These seven interrupt sources can be enabled individually by setting SFR INTMSK (bits 0−6). The
newly added interrupt at vector address 002BH is driven by the I²C circuit in the DDC port.
The interrupt enable control bits for the two interrupts at 0013H and 002BH are IE.2 and IE.5 in the IE
register, respectively. The interrupt priority control bits are IP.2 and IP.5 in the IP register. The
interrupts can be disabled by clearing IE.7 (disable all interrupts). For example, the programmer can
enable the A/D converter interrupt by the "MOV INTMSK, #00000010B" instruction. When the
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Publication Release Date: October 1996
Revision A1