W989D6CB Datasheet, PDF (30/67 Pages) Winbond – 512Mb Mobile LPSDR

W989D6CB / W989D2CB
512Mb Mobile LPSDR
8.5.7 CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of
CAS Latency depends on the frequency of CLK. The minimum value which satisfies the following formula must be set in this field.
A6
A5
A4
CAS Latency
0
1
0
2 clock
0
1
1
3 clock
 Reserved bits (A7, A8, A10, A11, A12, BA0, BA1)
These bits are reserved for future operations. They must be set to 0 for normal operation.
 Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are selected. When the A9 bit is
1, Burst Read and Single Write mode are selected.
A9
0
1
8.5.8 Mode Register Definition
A0
A1
A2
A3
A4
A5
A6
A07
A8
A09
A10
AA101
A12
BA0
BA1
Burst Length
Addressing Mode
CAS Latency
"0"
Reserved
"0"
Reserved
WriteAM0 ode
"0"
"0"
"0"
ResAe0rved
"0"
"0"
Write Mode
Burst Read and Burst Write
Burst Read and Single Write
A0
A2 A01 A0
0 A00 0
0 A00 1
0 A10 0
0 A10 1
1 A00 0
1 A00 1
1 A10 0
1 A10 1
A03
A00
A10
A6 A05 A4
0 A00 0
0 A00 1
0 A10 0
0 A10 1
1 A00 0
A09
A00
A10
BurstAL0ength
SequAe0ntial
InteArle0ave
1
A10
A20
A20
A40
A40
A80
A80
ResAe0rved
ResAe0rved
FuAll 0Page
AddressAin0g Mode
SequAe0ntial
InterAle0ave
CAS LAa0tency
ResAe0rved
Reserved
2
A30
Reserved
Single Write Mode
Burst read aAnd0 Burst write
Burst read anAd0single write
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Publication Release Date: Sep, 22, 2011
Revision A01-005