W989D6CB Datasheet, PDF (13/67 Pages) Winbond – 512Mb Mobile LPSDR

W989D6CB / W989D2CB
512Mb Mobile LPSDR
Note :
1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect deice reliability.
2. All voltages are referenced to VSS and VSSQ.
3. These parameters depend on the cycle rate. These values are measured at a cycle rate with the minimum values of tCK and tRC .
Input signals transition once per tCK period.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 9.
6. AC TEST CONDITIONS : (refer to 6.6.2)
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage
levels.
8. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as
follows: The number of clock cycles = specified value of timing / clock period (count fractions as a whole number)
9. Power up Sequence : The SDRAM should be powered up by the following sequence of operations.
a. Power must be applied to VDD before or at the same time as VDDQ while all input signals are held in the “NOP” state. The
CLK signal will be applied at power up with power.
b. After power-up a pause of at least 200 uA is required. It is required that DQM and CKE signals must be held “High” (VDD
levels ) to ensure that the DQ output is in High-impedance state.
c. All banks must be precharged.
d. The Mode Register Set command must be issued to initialize the Mode Register.
e. The Extended Mode Register Set command must be issued to initialize the Extended Mode Register.
f. Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
6.6.3 AC Latency Characteristics
CKE to clock disable (CKE Latency)
DQM to output in High-Z (Read DQM Latency)
DQM to input data delay (Write DQM Latency)
Write command to input data (Write Data Latency)
CS to Command input ( CS Latency)
Precharge to DQ Hi-Z Lead time
Precharge to Last Valid data out
Burst Stop Command to DQ Hi-Z Lead time
Burst Stop Command to Last Valid data out
Read with Auto Precharge Command to Active/Ref Command
Write with Auto Precharge Command to Active/Ref Command
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
1
2
0
0
0
2
3
1
2
2
3
1
2
BL+ tRP
BL+ tRP
BL+1 + tRP
BL+1 + tRP
Cycle
Cycle + ns
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Publication Release Date: Sep, 22, 2011
Revision A01-005