W9725G6KB25I-TR Datasheet, PDF (3/87 Pages) Winbond – 4M X 4 BANKS X 16 BIT DDR2 SDRAM

W9725G6KB
11.1 Command Input Timing.......................................................................................................................68
11.2 ODT Timing for Active/Standby Mode.................................................................................................69
11.3 ODT Timing for Power Down Mode ....................................................................................................69
11.4 ODT Timing mode switch at entering power down mode ....................................................................70
11.5 ODT Timing mode switch at exiting power down mode ......................................................................71
11.6 Data output (read) timing ....................................................................................................................72
11.7 Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................72
11.8 Data input (write) timing ......................................................................................................................73
11.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) ....................................................................73
11.10
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ......................................74
11.11
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4).........................................................74
11.12
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) .............................................................75
11.13
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) ..................................................75
11.14
Write operation with Data Mask: WL=3, AL=0, BL=4) ...............................................................76
11.15
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............77
11.16
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............77
11.17
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............78
11.18
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............78
11.19
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............79
11.20
Burst write operation followed by precharge: WL = (RL-1) = 3 ..................................................79
11.21
Burst write operation followed by precharge: WL = (RL-1) = 4 ..................................................80
11.22
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ...............80
11.23
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ...............81
11.24
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................81
11.25
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................82
11.26
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.................................82
11.27
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 .......................83
11.28
Self Refresh Timing ...................................................................................................................83
11.29
Active Power Down Mode Entry and Exit Timing.......................................................................84
11.30
Precharged Power Down Mode Entry and Exit Timing ..............................................................84
11.31
Clock frequency change in precharge Power Down mode ........................................................85
12.
PACKAGE SPECIFICATION ..............................................................................................................86
13.
REVISION HISTORY ..........................................................................................................................87
Publication Release Date: Sep. 03, 2012
-3-
Revision A03