W29GL128CH9C-TR Datasheet, PDF (3/67 Pages) Winbond – 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE

W29GL128C
Table of Contents
1
GENERAL DESCRIPTION ......................................................................................................... 1
2
FEATURES ................................................................................................................................. 1
3
PIN CONFIGURATION ............................................................................................................... 2
4
BLOCK DIAGRAM ...................................................................................................................... 3
5
PIN DESCRIPTION..................................................................................................................... 3
6
ARRAY ARCHITECTURE........................................................................................................... 4
6.1 Sector Address Table ..................................................................................................... 4
7
FUNCTIONAL DESCRIPTION.................................................................................................... 5
7.1 Device Bus Operation ..................................................................................................... 5
7.2 Instruction Definitions...................................................................................................... 6
7.2.1 Reading Array Data .......................................................................................................... 6
7.2.2 Page Mode Read .............................................................................................................. 6
7.2.3 Device Reset Operation .................................................................................................... 7
7.2.4 Standby Mode ................................................................................................................... 7
7.2.5 Output Disable Mode ........................................................................................................ 7
7.2.6 Write Operation.................................................................................................................7
7.2.7 Byte/Word Selection .........................................................................................................8
7.2.8 Automatic Programming of the Memory Array .................................................................. 8
7.2.9 Erasing the Memory Array ................................................................................................ 9
7.2.10 Erase Suspend/Resume ............................................................................................... 10
7.2.11 Sector Erase Resume ................................................................................................... 10
7.2.12 Program Suspend/Resume...........................................................................................11
7.2.13 Program Resume .......................................................................................................... 11
7.2.14 Write Buffer Programming Operation ............................................................................11
7.2.15 Buffer Write Abort .........................................................................................................12
7.2.16 Accelerated Programming Operation ............................................................................ 12
7.2.17 Automatic Select Bus Operation ................................................................................... 12
7.2.18 Automatic Select Operations......................................................................................... 13
7.2.19 Automatic Select Instruction Sequence ........................................................................ 13
7.2.20 Enhanced Variable IO (EVIO) Control .......................................................................... 14
7.2.21 Hardware Data Protection Options ............................................................................... 14
7.2.22 Inherent Data Protection ............................................................................................... 14
7.2.23 Power Supply Decoupling ............................................................................................. 14
7.3 Enhanced Sector Protect/Un-protect ............................................................................ 15
7.3.1 Lock Register .................................................................................................................. 16
7.3.2 Individual (Non-Volatile) Protection Mode ....................................................................... 17
7.4 Security Sector Flash Memory Region ......................................................................... 20
7.4.1 Factory Locked: Security Sector Programmed and Protected at factory.........................20
7.4.2 Customer Lockable: Security Sector Not Programmed or Protected .............................. 20
7.5 Instruction Definition Tables ......................................................................................... 21
7.6 Common Flash Memory Interface (CFI) Mode ............................................................. 25
7.6.1 Query Instruction and Common Flash memory Interface (CFI) Mode.............................25
8
ELECTRICAL CHARACTERISTICS ......................................................................................... 29
Publication Release Date: August 2, 2013
i
Revision H