W25Q80 Datasheet, PDF (27/61 Pages) Winbond – 8M-BIT, 16M-BIT AND 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q80, W25Q16, W25Q32
10.2.11 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO₀, IO₁, IO₂, and IO₃. A Quad enable of Status Register-2 must
be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit
QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the
W25Q80/16/32 at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in figure 11. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.
Figure 11. Fast Read Quad Output Instruction Sequence Diagram
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Publication Release Date: September 26, 2007
Preliminary - Revision B