W742C813 Datasheet, PDF (26/56 Pages) Winbond – 4 BIT MICROCONTROLLER

W742E/C813
5.15.1 Hold Mode Release Enable Flag (HEF, HEFD)
The hold mode release enable flag is organized on an 8-bit binary register (HEF.0 to HEF.7) and a 1-
bit register (HEFD). The HEF and HEFD are used to control the hold mode release conditions. It is
controlled by the MOV HEF, #I, MOV HEFD,#I instructions. The bit descriptions are as follows:
76543210
HEF w w w w w w w w
0
HEFD
w
Note: W means write only.
HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released.
HEF.2 = 1 Signal change at port RC causes Hold mode to be released.
HEF.3 = 1 Falling edge signal at port P1.2 (/INT0) causes Hold mode to be released.
HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released.
HEF.5 = 1 Serial I/O
HEF.6 = 1 Falling edge signal at port P1.3 (/INT1) causes Hold mode to be released.
HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.
HEFD = 1 Signal change at port RD causes Hold mode to be released.
5.15.2 Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as a 8-bit binary register (IEF.0 to IEF.7). These bits are used to
control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is occurred, the corresponding event flag will be clear, but the other bits are unaffected. In
interrupt subroutine, these interrupts will be disable till the instruction MOV IEF, #I or EN INT is
executed again. However, these interrupts can be disable by executing DIS INT instruction. The bit
descriptions are as follows:
76543210
IEF w w w w w w w w
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.
IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.
IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC.
IEF.3 = 1 Interrupt 3 is accepted by a falling edge signal at port P1.2 (/INT0).
IEF.4 = 1 Interrupt 4 is accepted by overflow from the Divider 1.
IEF.5 = 1 Interrupt 5 is accepted by Serial I/O signal
IEF.6 = 1 Interrupt 6 is accepted by a falling edge signal at port P1.3 (/INT1).
IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
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