W742C813 Datasheet, PDF (18/56 Pages) Winbond – 4 BIT MICROCONTROLLER

W742E/C813
We must remember that the X010B state is inhibitive, because it will induce the system shutdown.
The organization of the dual-clock operation mode is shown in
Figure 5-4.
HOLD
SCR.0
XIN1
XOUT1
Main Oscillator ^Fm
Fosc _{System Clock}
T1
T2
Fs
SCR.1 enable/disable
Generator
T3
T4
STOP
Divider 0
XIN2
XOUT2
Sub-oscillator
LCD Frequency
Selector
Divider 1
INT4
HCF.4
SCR : System clock Control Register ( default = 00H )
SCR.3(13/12 bit)
Bit3 Bit2 Bit1 Bit0
0 : Fosc = Fm
1 : Fosc = Fs
0 : Fm enable
1 : Fm disable
0 : WDT input clock is Fosc/2048
1 : WDT input clock is Fosc/16384
0 : 13 bit
1 : 12 bit
Daul clock operation mode :
- SCR.0=0, Fosc=Fm : SCR.0=1, Fosc=Fs
- Flcd=Fs, In STOP mode LCD is turned off.
F_LCD
Figure 5-4 Organization of the dual-clock operation mode
5.11 Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. The WDT can be enabled by mask option code. If the WDT overflows, the chip will be
reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be
switched to FOSC/16384 by setting SCR.2 register. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it
overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The
WDT overflow period is about 1S when the system clock (FOSC) is 32 KHz and WDT clock input is
FOSC/2048. The organization of the Divider0 and watchdog timer is shown in Figure 5-5. The minimum
WDT time interval is 1/(FOSC/16384 x 16) - 1/(FOSC/16384).
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