W742C813 Datasheet, PDF (17/56 Pages) Winbond – 4 BIT MICROCONTROLLER

W742E/C813
5.8 Sub-oscillator
The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the
32768 Hz crystal could be connected to XIN2 and XOUT2.
5.9 Dividers
Divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic interrupt.
When the main clock starts action, the Divider0 is incremented by each clock (FOSC). The main clock
can come from main oscillator or sub-oscillator by setting SCR register. When an overflow occurs, the
Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set
(IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the
hold state is terminated. And the last 4-stage of the Divider0 can be reset by executing CLR DIVR0
instruction. If the main clock is connected to the 32.768K Hz crystal, the EVF.0 will be set to 1
periodically at the period of 500 mS.
Divider 1 is orginized with 13/12 bits up-counter that only has sub-oscillator clock source. If the sub-
oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the
Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set
(IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1), the
hold state is terminated. And the last 4-stage of the Divider1 can be reset by executing CLR DIVR1
instruction. There are two period time (125 mS & 250 mS) that can be selected by setting the SCR.3
bit. When SCR.3 = 0 (default), the 250 mS period time is selected; SCR.3 = 1, the 125 mS period time
is selected.
5.10 Dual-clock Operation
In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system
clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation
is performed by setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is set to 0,
the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the
clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the main-
oscillator can stop oscillating when the SCR.1 is set to 1. When the main clock switch, we must care
the following cases:
1. X000B → X011B (FOSC = Fm→ FOSC = Fs): we should not exchange the FOSC from Fm into Fs and
disable Fm simultaneously. We could first exchange the FOSC from Fm into Fs, then disable the
main-oscillator. So it should be X000B→X001B→X011B.
2. X011B → X000B (FOSC = Fs→ FOSC = Fm): we should not enable Fm and exchange the FOSC from
Fs into Fm simultaneously. We could first enable the main-oscillator; the 2nd step is calling a delay
subroutine to wait the main-oscillator oscillating stabely; then exchange the FOSC from Fs into Fm is
the last step. So it should be X011B→X001B→delay the Fm oscillating stable time→X000B.
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Publication Release Date: December 2000
Revision A1