W9864G6IH_10 Datasheet, PDF (24/44 Pages) Winbond – 1M × 4BANKS × 16BITS SDRAM

W9864G6IH
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
RAS
CAS
WE
BS0
BS1
A10
RAa
tRCD
tRC
tRAS
tRP
RBb
tRCD
tRP
tRAS
RAc
tRCD
A0-A9,
RAa
A11
DQM
CKE
DQ
CAx
RBb
CBy
RAc
CAz
tAC
tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1
tRRD
tRRD
tAC
by4 by5 by6 by7
CZ0
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
Read
Precharge
Active
Read
Precharge
Active
Read
Precharge
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Publication Release Date: Mar. 22, 2010
Revision A11