W25Q64BV Datasheet, PDF (20/61 Pages) Winbond – 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q64BV
11.2.4 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and
Write Status Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the
instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
Figure 4. Write Enable Instruction Sequence Diagram
11.2.5 Write Disable (04h)
The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase
instructions.
Figure 5. Write Disable Instruction Sequence Diagram
- 20 -